Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation Application of DivisionalApplication Ser. No. 13/240,983, filed Sep. 22, 2011, which claimspriority of U.S. patent application Ser. No. 12/318,504, filed Dec. 30,2008, which claims priority of Korean patent application number10-2008-0047082, filed on May 21, 2008, which is incorporated herein byreference in its entirety.

BACKGROUND

The present application relates to a semiconductor device and a methodfor fabricating the same.

In order to obtain a required capacitance in a limited area, a metallayer such as a titanium nitride (TiN) layer has been used as anelectrode of a capacitor e.g., a storage node (SN)), and ametal-insulator-metal (MIM) capacitor having a three-dimensionalstructure such as a cylinder or concave structure.

FIGS. 1A and 1B illustrate a method for fabricating a storage node of atypical semiconductor device, and FIG. 2 is a micrographic viewillustrating limitations of the typical semiconductor device.

Referring to FIG. 1A, a first interlayer insulation layer 12 having afirst storage node contact plug 13 is formed over a substrate 11 where apredetermined structure is formed, and a second interlayer insulationlayer 14 is formed over the first interlayer insulation layer 12.

A second storage node contact plug 15 penetrates the second interlayerinsulation layer 14 to contact with a top surface of the first storagenode contact plug 13.

An etch stop layer 16 and a separation insulation layer 17 aresequentially formed over the second interlayer insulation layer 14, anda storage node hole 18 is formed by sequentially etching the separationinsulation 17 and the etch stop layer 16 in order to expose a topsurface of the second storage node contact plug 15.

A barrier metal layer (not shown) is formed along a surface of thestorage node hole 18, and a thermal treatment process is performed toform an ohmic contact layer 19 over the second storage node contact plug15.A storage node 20 is formed in the storage node hole 18.

Referring to FIG. 1B, the remaining separation insulation layer 17 isremoved through a wet dip-out process to form the storage node 20 havinga cylindrical type.

However, when the first interlayer insulation layer 12, the secondinterlayer insulation layer 14, and the separation insulation layer 17are formed of an oxide layer, the second interlayer insulation layer 14under the storage node 20 is etched to penetrate the storage node 20through a chemical etchant during a wet dip-out process, as indicated by“A” in FIGS. 1B and 2. Thus, a defect such as a bunker 21 can occur.This bunker 21 generates a bridge between adjacent storage nodes 20 tocause a dual bit failure. Due to the bunker 21, an electrical shortcircuit phenomenon occurs between a metal interconnection and thestorage node 20 during a subsequent metal interconnection process, ordefective patterns may be formed during a mask process for forming themetal interconnection.

Additionally, since the degree of integration in a semiconductor deviceis increasing, a cell area where a capacitor may be formed is reducedand thus an aspect ratio of the storage node 20 is increased to obtain asufficient electrostatic capacity in a limited cell area. Since thestorage node 20 with a high aspect ratio causes deterioration of stepcoverage during a subsequent dielectric formation process, a fabricatingyield of a semiconductor device is decreased. To overcome theabove-mentioned limitations, a method for forming the thin storage node20 of less than 300 Å is provided, but if the thickness of the storagenode 20 is reduced, limitations due to the bunker 21 become worsebecause a chemical etchant penetrates more easily during a wet dip-outprocess.

SUMMARY

Embodiments of a semiconductor device are directed to preventing adefect such as a bunker.

In addition, embodiments are directed to providing a semiconductordevice having a storage node with a thickness of less than 300 Å.

Moreover, embodiments are directed to providing a semiconductor devicecapable of increasing electrostatic capacity of a capacitor.

In accordance with at least one aspect, a semiconductor device includes:a first storage node contact plug penetrating a first interlayerinsulation layer and partially protruding above the first interlayerinsulation layer; a second storage node contact plug contacting thefirst storage node contact plug that protrudes above the firstinterlayer insulation layer; a storage node contacting a top surface ofthe second storage node contact plug; and a second interlayer insulationlayer formed over the first interlayer insulation layer, the secondinterlayer insulation layer surrounding an outer sidewall at a bottomregion of the first storage node, the first storage node contact plugprotruding above the first interlayer insulation layer, and the secondstorage node contact plug.

In some embodiments, the first interlayer insulation layer includes anoxide layer and the second interlayer insulation layer comprises anitride layer. The thickness of the second interlayer insulation layermay be less than that of the first interlayer insulation layer.

In some embodiments, the first storage node contact plug and the secondstorage node contact plug are formed of the same material, and the firststorage node contact plug and the second storage node contact plugincludes a polysilicon layer. The second storage node contact plug mayhave a zigzag structure where the second storage node contact plugoverlaps the first storage node contact plug by a predetermined region.

The storage node may In some embodiments include any one of the groupconsisting of titanium nitride (TiN), tantalum nitride (TaN), hafniumruthenium (HfN), ruthenium (Ru), ruthenium oxide (RuO₂), platinum (Pt),iridium (Ir), and iridium oxide (IrO₂), or a stack layer thereof.

In some embodiments the semiconductor device further includes an ohmiccontact layer between the second storage node contact plug and thestorage node. The ohmic contact layer may include metal silicide.

In accordance with another embodiment, a method for fabricating asemiconductor device includes: forming a storage node contact plug thatpenetrates an interlayer insulation layer; forming a separationinsulation layer over the interlayer insulation layer; performing a mainetch process to form an open region by selectively etching theseparation insulation layer, the open region exposing a top surface ofthe storage node contact plug; performing an over-etch process to expandthe open region by etching the storage node contact plug by apredetermined thickness at a bottom of the open region; forming astorage node in the open region; and removing the separation insulationlayer. In some embodiments the main etch process and the over-etchprocess are performed in-situ.

The forming of the storage node contact plug may include: forming afirst interlayer insulation layer that includes a first storage nodecontact plug; partially protruding the first storage node contact plugabove the first interlayer insulation layer by recessing the firstinterlayer insulation layer; forming a second interlayer insulationlayer to cover the first storage node contact plug that protrudes abovethe first interlayer insulation layer; forming a contact hole topartially expose the first storage node contact plug by selectivelyetching the second interlayer insulation layer; and forming a secondstorage node contact plug by filling the contact hole with a conductivelayer.

In some embodiments, the first interlayer insulation layer and theseparation insulation layer includes an oxide layer and the secondinterlayer insulation layer includes a nitride layer, wherein thethickness of the second interlayer insulation layer is, In someembodiments, less than a thickness of the first interlayer insulationlayer.

The second storage node contact plug may have a zigzag structure wherethe second storage node contact plug overlaps the first storage nodecontact plug by a predetermined region. The first storage node contactplug and the second storage node contact plug may be formed of the samematerial. The first storage node contact plug and the second storagenode contact plug may include a polysilicon layer.

The etch depth during the performing of the over-etch process may beless than a thickness of the second interlayer insulation layer.

In some embodiments the storage node includes one selected from thegroup consisting of titanium nitride (TiN), tantalum nitride (TaN),hafnium ruthenium (HfN), ruthenium (Ru), ruthenium oxide (RuO₂),platinum (Pt), iridium (Ir), and iridium oxide (IrO₂), or a stack layerthereof.

The method may further include forming an ohmic contact layer betweenthe storage node contact plug and the storage node. The ohmic contactlayer may include metal silicide.

In accordance with at least one other embodiment, a method forfabricating a capacitor of a semiconductor device, incldues: forming afirst interlayer insulation layer that includes a first storage nodecontact plug; partially protruding the first storage node contact plugabove the first interlayer insulation layer by recessing the firstinterlayer insulation layer; forming a second interlayer insulationlayer over the first interlayer insulation layer to cover the protrudingfirst storage node contact plug; forming a contact hole to expose thefirst storage node contact plug by selectively etching the secondinterlayer insulation layer; forming a second storage node contact plugby filling the contact hole with a conductive layer; forming aseparation insulation layer over the second interlayer insulation layerthat includes the second storage node contact plug; forming an openregion by selectively etching the separation insulation layer and thesecond storage node contact plug; forming a storage node in the openregion; and removing the separation insulation layer.

The first interlayer insulation layer and the separation insulationlayer may include an oxide layer and the second interlayer insulationlayer comprises a nitride layer.

In at least one embodiment, the forming of the open region includes:performing a main etch process to form an open region by selectivelyetching the separation insulation layer, the open region exposing a topsurface of the second storage node contact plug; and performing anover-etch process to expand the open region by partially etching thesecond storage contact plug at a bottom of the open region. The etchdepth during the over-etch process may be less than a thickness of thesecond interlayer insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a method for fabricating a storage node of atypical semiconductor device.

FIG. 2 is a micrographic view illustrating a limitation of the typicalsemiconductor device.

FIG. 3 is a cross-sectional view of a semiconductor device in accordancewith at least one embodiment.

FIGS. 4A to 4G illustrate a method for fabricating a semiconductordevice in accordance with the at least one embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

Other objects and advantages can be understood by the followingdescription, and become apparent with reference to the followingdisclosed embodiments.

In the figures, the dimensions of layers and regions are exaggerated forclarity of illustration. It will also be understood that when a layer(or film) is referred to as being ‘on’ another layer or substrate, itcan be directly on the other layer or substrate, or intervening layersmay also be present. Further, it will be understood that when a layer isreferred to as being ‘under’ another layer, it can be directly under,and one or more intervening layers may also be present. In addition, itwill also be understood that when a layer is referred to as being‘between’ two layers, it can be the only layer between the two layers,or one or more intervening layers may also be present.

Disclosed embodiments are of a semiconductor device and fabricationmethod capable of preventing a dual bit failure caused by defects suchas a bunker in a capacitor.

The methods prevent a chemical etchant from penetrating a firstinterlayer insulation layer during a wet dip-out process. A secondinterlayer insulation layer providing a sidewall of a second storagenode contact plug is formed of a material having a lower etch rate withrespect to a first interlayer insulation layer, providing a sidewall ofa first storage node contact plug and a separation insulation layerproviding a sidewall of an open region (i.e., a storage node hole forforming a storage node), and also the second interlayer insulation layersurrounds the outer sidewall of a bottom region of a storage node.

FIG. 3 is a cross-sectional view of a semiconductor device in accordancewith at least one embodiment and depicts a first interlayer insulationlayer 32, a first storage node contact plug 33, a second storage nodecontact plug 35, a storage node 42, and a second interlayer insulationlayer 34. The first interlayer insulation layer 32 is formed over asubstrate 31. The first storage node contact plug 33 penetrates thefirst interlayer insulation layer 32 and a portion of the first storagenode contact plug 33 protrudes over the first interlayer insulationlayer 32.

The second storage node contact plug 35 over the first interlayerinsulation layer 32 contacts the first storage node contact plug 33protruding above the first interlayer insulation layer 32. The storagenode 42 contacting a top surface of the second storage node contact plug35. The second interlayer insulation layer 34 over the first interlayerinsulation layer 32 surrounds the outer sidewall at the bottom region ofthe storage node 42, the second storage node contact plug 35, and thefirst storage node contact plug 33 protruding over the first interlayerinsulation layer 32. Additionally, in some embodiments the semiconductordevice includes an ohmic contact layer 41 interposed between the secondstorage node contact plug 35 and the storage node 42.

The first interlayer insulation layer 32 is formed of an oxide layerselected from the group consisting of silicon oxide (SiO₂), BoronPhosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), TetraEthyle Ortho Silicate (TEOS), Un-doped Silicate Glass (USG), Spin OnGlass (SOG), High Density Plasma (HDP), and Spin On Dielectric (SOD), ora stack layer thereof. The first interlayer insulation layer 32 may beformed of a stack layer where a SOD layer having excellent gap-fillcharacteristic and a HDP layer having excellent quality layer aresequentially stacked.

The second interlayer insulation layer 34 includes the second storagecontact plug 35 to align the storage node 42 with the first storage nodecontact plug 33. The storage node 42 is aligned in a zigzag form on thesecond interlayer insulation layer 34. Accordingly, the secondinterlayer insulation layer 34 may be filled between the protrudingfirst storage node contact plugs 33 and may cover the top surface of thefirst storage node contact plug 33 with a thickness betweenapproximately 1,000 Å to approximately 1,500 Å.

In some embodiments, the second interlayer insulation layer 34 is formedthinner than the first interlayer insulation layer 32.

The second interlayer insulation layer 34 may be formed of a materialhaving a lower etch rate with respect to the first interlayer insulationlayer 32 in order to simplify fabricating processes of a semiconductordevice. For example, if the first interlayer insulation layer 32 isformed of an oxide layer, the second interlayer insulation layer 34 maybe formed of a nitride layer having a lower etch rate with respect tothe oxide layer. A silicon nitride layer (Si₃N₄) may be used as anitride layer. At this point, because the second interlayer insulationlayer 34 is formed of a material having a lower etch rate with respectto the first interlayer insulation layer 32, in some embodiments an etchstop layer forming process is to protect the bottom structure of thestorage node 42 during a wet dip-out process. Moreover, a bunker may beprevented from occurring in the first interlayer insulation layer 32 bypreventing a chemical etchant from penetrating the first interlayerinsulation layer 32 during the wet dip-out process.

Since the second interlayer insulation layer 34 has a structuresurrounding an outer sidewall at the bottom region of the storage node42, the storage node 42 does not collapse and a chemical etchant can beprevented from penetrating the first interlayer insulation layer 32.

The first storage node contact plug 33 is electrically connected to apredetermined region of the substrate 31 e.g., a landing plug (notshown), and serves to electrically connects a capacitor with a structureof the substrate 31.

The first storage node contact plug 33 protrudes by a thickness ofapproximately 500 Å to approximately 1,000 Å on the top surface of thefirst interlayer insulation layer 32 in order to increase a contact areafor the second storage node contact plug 35.

As a semiconductor device becomes highly integrated, in order to form acapacitor in a limited area, in some embodiments, the second storagenode contact plug 35 connects the storage node 42 with the first storagenode contact plug 33 electrically and aligns them simultaneously.Additionally, the storage node 42 are arranged in a zigzag pattern, andthe second storage node contact plug 35 may be formed in a zigzagpattern to overlap a predetermined region of the first storage nodecontact plug 33.

In some embodiments the first storage node contact plug 33 and thesecond storage node contact plug 35 are formed of the same material.This reason is to prevent a potential barrier from occurringtherebetween. For reference, if the first storage node contact plug 33and the second storage node contact plug 35 are formed of differentmaterials, a potential barrier therebetween occurs and due to thepotential barrier, charge transfer does not smoothly occurs. That is,due to the formed potential barrier, signal transmission therebetween isdelayed such that electrical characteristics of a semiconductor devicecan be deteriorated.

The first storage node contact plug 33 and the second storage nodecontact plug 35 may be formed from one of a polysilicon layer, a metalmaterial layer, and a conductive organic layer. In some embodiments, themetal material layer is formed of one of gold (Au), tungsten (W),aluminum (Al), titanium nitride (TiN), iridium oxide (IrO₂), Indium TinOxide (ITO), and Indium Zinc Oxide (IZO). The conductive organic layermay be formed of one of pentacene, tetracene, and anthracene. The firststorage node contact plug 33 and the second storage node contact plug 35may be formed of a polysilicon layer, which has an excellent interfacecharacteristic with respect to a semiconductor material and is easilyused for a formation process.

Additionally, since the second storage node contact plug 35 has astructure contacting the first storage node contact plug 33 protrudingabove the first interlayer insulation layer 32, a contact area betweenthe first storage node contact plug 33 and the second storage nodecontact plug 35 can be increased and contact resistance therebetween canalso be decreased.

In some embodiments, the storage node 42 is a cylindrical form formed ofa staked layer where a barrier metal layer 39 and a conductive layer 40for a storage node are sequentially stacked. In some embodiments, thestorage node 42 has a structure where the barrier metal layer 39surrounds the outer sidewall of the conductive layer for storage node 40having a cylindrical form. At this point, the barrier metal layer 39 mayhave a thickness of approximately 20 Å to approximately 100 Å, and theconductive layer for storage node 40 may have a thickness ofapproximately 100 Å to approximately 500 Å. The storage node 42 may havea thickness of less than 300 Å (e.g., approximately 100 Å toapproximately 300 Å) in order to increase electrostatic capacitance of acapacitor.

The barrier metal layer 39 serves to prevent mutual diffusion between amaterial of the conductive layer for a storage node 40 and a material ofthe second storage node contact 35, and also provides an ohmic contactlayer 41 to reduce a contact resistance between the storage node 42 andthe second storage node contact plug 35.

In some embodiments, the barrier metal layer 39 may be formed of one ofrefractory metals such as titanium (Ti), cobalt (Co), molybdenum (Mo),platinum (Pt), iridium (Ir), ruthenium (Ru), chrome (Cr), tantalum (Ta),and zirconium (Zr).

The conductive layer 40 for a storage node may be formed of at least onemetal material selected from the group consisting of titanium nitride(TiN), tantalum nitride (TaN), hafnium nitride (HfN), ruthenium (Ru),ruthenium oxide (RuO₂), platinum (Pt), iridium (Ir), and iridium oxide(IrO₂), or a stack layer thereof.

The ohmic contact layer 41 interposed between the second storage nodecontact plug 35 and the storage node 42 serves to reduce a contactresistance therebetween. In some embodiments, the ohmic contact layer 41is formed of metal salicide through reaction between the second storagenode contact plug 35 formed of polysilicon and the barrier metal layer39 during a thermal treatment process. For example, if the barrier metallayer 39 is formed of titanium (Ti), the ohmic contact layer 41 may beformed of titanium silicide (TiSi₂).

Since the second interlayer insulation layer 34 is formed of a materialhaving a lower etch rate with respect to the first interlayer insulationlayer 32, there is no necessary to additionally form an etch stop layerin order to protect the bottom structure of a storage node 42 during awet dip-out process. Therefore, the present invention can simplifyfabricating processes of a semiconductor device.

Since the second interlayer insulation layer 34 is formed of a materialhaving a lower etch rate selectivity with respect to the firstinterlayer insulation layer 32, a defect such as a bunker can beprevented during a wet deep out process without the forming of theadditional etch stop layer. Therefore, limitations due to a bunker,e.g., an electrical short circuit phenomenon between the metalinterconnection and the storage node 42, defective pattern occurrenceduring a mask process for forming a metal interconnection, and dual bitfailure due to a bridge between adjacent storage nodes 42, can beprevented.

Because a defect such as a bunker can be prevented using the abovedisclosed process, the thickness of the storage node 42 can be reduced.Therefore, a step coverage can be obtained on the storage node 42 duringa dielectric formation process and electrostatic capacitance of acapacitor can be improved by increasing the inner hole area of thestorage node 42.

Because the second interlayer insulation layer 34 is formed to surroundthe outer sidewall at the bottom region of the storage node 42, thestorage node 42 does not collapse during a wet dip-out process.

Moreover, since the first storage node contact plug 33 protrudes abovethe first interlayer insulation layer 32 in order to increase a contactarea between the first storage node contact plug 33 and the secondstorage node contact plug 35, a contact resistance therebetween can bedecreased, thereby improving an electrical characteristic of asemiconductor device.

Therefore, since a necessary electrostatic capacitance in a limited areaof a capacitor in a semiconductor device can be obtained and a bunkerformation can be prevented, reliability and a fabricating yield of thecapacitor can be improved.

FIGS. 4A to 4G illustrate one embodiment of a method for fabricating asemiconductor device as described above.

Referring to FIG. 4A, a first interlayer insulation layer 32 is formedon a substrate 31 having a predetermined structure, and a first storagenode contact plug 33 is formed to be electrically connected to apredetermined area of the substrate 31 through the first interlayerinsulation layer 32.

In some embodiments, the first interlayer insulation layer 32 is formedof one of SiO2, BPSG, PSG, TEOS, USG, SOG, HDP, and SOD, or a stacklayer thereof. The first interlayer insulation layer 32 may be formed ofa stack layer where a SOD layer having excellent gap-fill characteristicand a HDP layer having excellent quality layer are sequentially stacked.

The first storage node contact plug 33 may include one of a polysiliconlayer, a metal material layer, and a conductive organic layer. The metalmaterial layer may be formed of Au, W, Al, TiN, IrO₂, ITO, or IZO. Theconductive organic layer may be formed of pentacene, tetracene, oranthracene. The first storage node contact plug 33 may be formed of apolysilicon layer, which has an excellent interface characteristic withrespect to a semiconductor material and is easily used for a formationprocess.

Although not illustrated, before the first interlayer insulation layer32 is formed, a transistor including a word line, a landing plug, and abit line are formed on the substrate 31.

The first interlayer insulation layer 32 is recessed to partiallyprotrude the first storage node contact plug 33 over the firstinterlayer insulation layer 32. At this point, the first interlayerinsulation layer 33 may be recessed by a depth of approximately 500 Å toapproximately 1,000 Å with respect to the top surface of the firststorage node contact plug 33. The recessing process can be performedthrough a wet etch process using a buffered oxide etchant (BOE) solutionor a hydrofluoric acid (HF) solution.

More specifically, the first storage node contact plug 33 partiallyprotrudes above the first interlayer insulation layer 32 byapproximately 500 Å to approximately 1,000 Å through the above mentionedprocess. In this way, a portion of the first storage node contact plug33 protrudes over the first interlayer insulation layer 32 in order toincrease a contact area between a second storage node contact plug,which will be formed through the subsequent process, and the firststorage contact plug 33, such that a contact resistance therebetween canbe reduced.

Referring to FIG. 4B, a second interlayer insulation layer 34 is formedon the first interlayer insulation layer 32 to cover the protrudingfirst storage node contact plug 33. At this point, the second interlayerinsulation layer 34 provides the sidewall of the second storage contactplug 35 in order for alignment between the first storage node contactplug 33 and the storage node, which will be aligned in a zigzag formthrough the subsequent process. Accordingly, the second interlayerinsulation layer 34 may be filled between the protruding first storagenode contact plugs 33 and may cover the top surface of the first storagenode contact plug 33 with a thickness between approximately 1,000 Å toapproximately 1,500 Å.

In some embodiments, second interlayer insulation layer 34 is formedthinner than the first interlayer insulation layer 32.

In order to simplify a fabricating process of a semiconductor device, insome embodiments, the second interlayer insulation layer 34 may beformed of a material having a lower etch rate with respect to the firstinterlayer insulation layer 32. For example, if the first interlayerinsulation layer 32 is formed of an oxide layer, the second interlayerinsulation layer 34 may be formed of a nitride layer having a lower etchrate with respect to the oxide layer. The nitride layer may includeSi₃N₄.

In some embodiments, an etch stop layer of a nitride layer, i.e., anopen region for forming the subsequent storage node, is formed on thesecond interlayer insulation layer 34 in order to protect a structureformed below the open region during a storage node hole forming process.Because the second interlayer insulation layer 34 is formed of amaterial having a lower etch rate with respect to the first interlayerinsulation layer 32, the second interlayer insulation layer 34 serves asan etch stop layer to protect the bottom structure of the open regionduring the forming of the open region. Accordingly, at least someembodiments do not require an additional etch stop layer formingprocess, thereby simplifying a fabricating process of a semiconductordevice.

On the other hand, due to the first storage node contact plug 33protruding above the first interlayer insulation layer 32, a heightdifference may be formed on the top surface of the second interlayerinsulation layer 34. Since this height difference has a negativeinfluence on the subsequent process, it needs to be removed through aplanarization process. At this point, the planarization process can beperformed through chemical mechanical polishing (CMP) or an etch backprocess.

The second interlayer insulation layer 34 is selectively etched to forma contact hole for a second storage contact plug that partially exposethe first storage node contact plug 33 protruding above the firstinterlayer insulation layer 32. A second storage node contact plug 35 isformed by filling the contact hole with a conductive layer. At thispoint, the second storage node contact plug 35 may be formed in a zigzagform to overlaps the first storage node contact plug 33 by apredetermined region. The second storage node contact plug 35 serves foralignment between the first storage node contact plug 33 and a storagenode, which will be aligned in a zigzag form.

Because the second storage node contact plug 35 is formed to contact thefirst storage node contact plug 33 protruding above the first interlayerinsulation layer 32, a contact area between the first storage nodecontact plug 33 and the second storage node contact plug 35 can beincreased, thereby reducing a contact resistance therebetween.

Moreover, the second storage node contact plug 35 may be formed of oneof the groups including a polysilicon layer, a metal material layer, anda conductive organic layer. The second storage node contact plug 35 maybe formed of the same material (i.e., a polysilicon layer) as the firststorage node contact plug 33. In this way, a contact resistance betweenthe first storage node contact plug 33 and the second storage nodecontact plug 35 can be more reduced. This is because that there is nopotential barrier therebetween because they are formed of the samematerial.

Referring to FIG. 4C, a separation insulation layer 36 is formed on thesecond interlayer insulation layer 34. At this point, the separationinsulation layer 36 provides a three-dimensional structure where astorage node will be formed and may be formed with a thickness ofapproximately 10,000 Å to approximately 30,000 Å.

The separation insulation layer 36 may be formed of a material having anetch selectivity with respect to the second interlayer insulation layer34. If the second interlayer insulation layer 34 is formed of a nitridelayer, the separation insulation layer 36 may be formed of an oxidelayer having an etch selectivity with respect of the nitride layer. Morespecifically, in some embodiments, the separation insulation layer 36 isformed of one of SiO₂, BPSG, PSG, TEOS, USG, SOG, HDP, and SOD, or astack layer thereof.

An etch barrier pattern 37 is formed on the separation insulation layer36 in order to form an open region. The etch barrier pattern 37 may beformed of one selected from the group consisting of an oxide layer, anitride layer, an oxide nitride layer, and an amorphous carbon layer, ora stack layer thereof.

Referring to FIG. 4D, a main etch process is performed to etch theseparation insulation layer 36 by using the etch barrier pattern 37 asan etch barrier and thus an open area 38 is formed to expose the topsurface of the second storage node contact plug 35. In some embodiments,the main etch process is performed through a plasma etch process, usingfor example, an oxide layer as an etch target for separation insulationlayer 36.

For example, if the main etch process is performed using a plasma etchmethod, one of plasma of gas mixed with methane fluoride gas, carbonfluoride gas, and argon gas, plasma of gas mixed with carbon fluoridegas and hydrogen gas (H₂), and plasma of gas mixed with methane fluoridegas, carbon dioxide gas (CO₂) can be used. Herein, the carbon fluoridegas includes CF₄, C₂F₆, and C₃F₈, and the methane fluoride gas includesCHF₃.

Referring to FIG. 4E, by using the etch barrier pattern 37 as an etchbarrier, an over-etch process is performed to etch the second storagenode contact plug 35 at the bottom surface of the open region 38 inorder to expand the open region 38. A reference number 38A refers to theexpanded open region.

The over-etch process is performed to allow the second interlayerinsulation layer 34 to surround the outer sidewall at the bottom regionof the storage node that is formed through the subsequent process, suchthat the storage node does not collapse during a wet dip-out process.Here, the second interlayer insulation layer 34, which is expose due tothe open region 38 during the over-etch process, may be etched with apredetermined thickness in addition to the second storage node contactplug 35.

During the over-etch process, an etch depth may be less than thethickness of the second interlayer insulation layer 34 in order toprevent the first interlayer insulation layer 32 from being exposed. Theover-etch process may be performed with an etch depth of approximately300 Å to approximately 500 Å with respect to the top surface of thesecond interlayer insulation layer 34. The reason of this process is toprevent a defect such as a bunker during the subsequent insulation layerremoving process, i.e., a wet dip-out process.

The over-etch process may be performed in-situ through the same etchingmethod and etching gas as the main etching process. At this point, sincethe main etch process is performed targeting the oxide layer, the secondinterlayer insulation layer 34 may have an etch depth different fromthat of the second storage node contact plug 35 during the over-etchprocess. However, since the etch depth is very small in a range fromapproximately 300 Å to approximately 500 Å, even if there an etch depthdifference in the second interlayer insulation layer 34 and the secondstorage node contact plug 35, i.e., there is a height differencetherebetween, it does not affect characteristics of a semiconductordevice.

The etch barrier pattern 37 is removed. In some embodiments, the etchbarrier pattern 37 is completely removed while the main etch andover-etch processes are performed. In other embodiments, if the etchbarrier pattern 37 remains after performing the main etch and over-etchprocesses, it is removed through an additional removing process and thenthe subsequent process may proceed.

Referring to FIG. 4F, a barrier metal layer 39 is formed along thesurface of the separation insulation layer 36 and the open region 38A.The barrier metal layer 39 serves to prevent mutual diffusion between amaterial constituting a storage node that will be formed through thesubsequent process and a material constituting the second storage nodecontact plug 35.

In some embodiments, the barrier metal layer 39 is formed of arefractory metal such as Ti, Co, Mo, Pt, Ir, Ru, Cr, Ta, and Zr.Additionally, the barrier metal layer 39 may be formed with a thicknessof approximately 20 Å to approximately 100 Å.

In order to reduce a contact resistance between the second storage nodecontact plug 35 and the storage node that will be formed through thesubsequent process, an ohmic contact layer 41 is formed on the interfacewhere the second storage node contact plug 35 and the barrier metallayer 39 contact. That is, the ohmic contact layer 41 is formed on thesecond storage node contact plug 35.

The ohmic contact layer 41 may be formed of metal silicide, e.g., TiSi2by reaction between the second storage contact plug 35 formed of apolysilicon layer and the barrier metal layer 39 formed of a refractivemetal layer, e.g., a titanium layer, through a thermal treatmentprocess. At this point, the thermal treatment process for forming theohmic contact layer 41 may be performed for approximately 10 seconds toapproximately 300 seconds at a temperature of approximately 700° C. toapproximately 900° C. under a nitrogen (N₂) atmosphere through rapidthermal anneal (RTA).

A conductive layer 40 for a storage node is formed on the barrier metallayer 39 along the surface of the separation insulation layer 36 and theopen region 38A. At this point, the conductive layer 40 for a storagenode may be formed of at least one metal selected from the groupconsisting of TiN, TaN, HfN, Ru, RuO₂, Pt, Ir, and IrO₂, or a stacklayer thereof. Additionally, the conductive layer 40 for a storage nodemay be formed with a thickness of approximately 100 Å to approximately500 Å.

In order to increase an electrostatic capacitance of a capacitor, thesum of thicknesses of the barrier metal layer 39 and the conductivelayer 40 for a storage node may be formed less than approximately 300 Å,e.g., between approximately 100 Å and approximately 300 Å.

The above mentioned barrier metal layer 39 and the conductive layer 40for a storage node may be formed through Chemical Vapor Formation (CVD)or Atomic Layer Formation, (ALD).

Referring to FIG. 4G, the conductive layer for storage node 40 and thebarrier metal layer 39 formed on the separation insulation layer 36 areremoved in order to expose the top surface of the separation insulationlayer 36, such that a storage node 42 is formed by performing a storagenode separation process for separating adjacent storage nodes 42. Thatis, the storage node 42 has a structure where the barrier metal layer 39and the conductive layer 40 for a storage node are stacked.

The storage node separation process may be performed through a CMP orblanket-etch process. If the storage node separation process isperformed through the blanket-etch process, the blanket-etch process isperformed to prevent the damage of the bottom of the storage node 42after the open region 38A is filled with a sacrificial layer.

A thermal treatment process is performed to improve a quality of thestorage node 42. At this point, the thermal treatment process isperformed for approximately 10 minutes to approximately 30 minutes undera nitrogen (N₂) atmosphere at a temperature of approximately 550° C. toapproximately 650° C. in a furnace.

The remaining insulation layer 36 is then removed through a wet dip-outprocess to complete the formation of the cylindrical storage node 42. Atthis point, a BOE solution or a HF solution is used as chemical etchantduring the wet dip-out process.

Even if no additional etch stop layer is formed, the second interlayerinsulation layer 34 serves as the etch stop layer. Therefore, the bottomstructure of the storage node 42 is not damaged during a wet dip-outprocess.

Since the second interlayer insulation layer 34 surrounds the outersidewall at the bottom region of the storage node 42, even when achemical etchant penetrates the storage node 42 during a wet dip-outprocess, the chemical etchant does not contact the first interlayerinsulation layer 32 because of the second interlayer insulation layer34. In this way, a bunker does not occur in the first interlayerinsulation layer 32.

In cases of a path A of when the chemical etchant penetrates along theouter sidewall of the storage node 42 and a path B of when it penetratesthe bottom of the storage node 42 that the second storage node contactplug 35 does not contact, since the second interlayer insulation layer34 surrounds the outer sidewall at the bottom region of the storage node42, its penetration path is increased, such that the chemical etchantdoes not penetrate the first interlayer insulation layer 32.

Additionally, because the second interlayer insulation layer 34surrounds the outer sidewall at the bottom region of the storage node42, the second interlayer insulation layer 34 supports the storage node42 during the wet dip-out process, such that the storage node 42 doesnot collapse.

Although not illustrated, a dielectric is formed on the entire surfaceof the storage node 42. At this point, the dielectric is formed from oneof ZrO₂, TaON, Ta₂O₅, TiO₂, Al₂O₃, HfO₂, SrTiO₃, and (Ba,Sr)TiO₃, or astack layer thereof through CVD or ALD.

A plate electrode is formed on the dielectric. At this point, the plateelectrode is formed of at least one metal selected from the groupconsisting of TiN, TaN, HfN, Ru, RuO₂, Pt, Ir, and IrO₂, or a stacklayer thereof.

Because no additional etch stop layer is formed in order to protect thebottom structure of the storage node 42 during a wet dip-out process,and because the second interlayer insulation layer 34 serves as an etchstop layer, fabricating processes of a semiconductor device can besimplified.

Moreover, since the second interlayer insulation layer 34 is formed of amaterial having a lower etch rate with respect to the first interlayerinsulation layer 32 and the separation insulation layer 36, a bunkerdoes not occur during a wet dip-out process. Therefore, limitations dueto a bunker can be prevented.

Because a defect such as a bunker can be prevented, the thickness of thestorage node 42 can be reduced. Therefore, a step coverage can beensured on the storage node 42 during a dielectric formation process andan electrostatic capacitance of a capacitor can be improved byincreasing the inner hole area of the storage node 42.

Additionally, since the second interlayer insulation layer 34 is formedto surround the outer sidewall of the bottom region of the storage node42, such that the storage node 42 does not collapse during a wet dip-outprocess.

Moreover, since the first storage node contact plug 33 protrudes abovethe first interlayer insulation layer 32 in order to increase a contactarea between the first storage node contact plug 33 and the secondstorage node contact plug 35, a contact resistance therebetween isdecreased, thereby improving an electrical characteristic of asemiconductor device.

Consequently, because a required electrostatic capacitance in a limitedarea of a capacitor of a semiconductor device can be obtained and defectformation such as a bunker can be prevented, reliability and afabricating yield of the capacitor can be improved.

In accordance with the embodiments of the present invention, because asecond interlayer insulation layer is formed of a material having alower etch rate with respect to a first interlayer insulation layer anda separation insulation layer, it is unnecessary to additionally form anetch stop layer in order to protect the bottom structure of a storagenode during a wet dip-out process. Therefore, a semiconductor devicefabricating process can be simplified.

In addition, because a second interlayer insulation layer serves as anetch stop layer, damage of a first interlayer insulation layer can beprevented during a wet dip-out process, such that a bunker formation canbe prevented. Therefore, limitations caused due to a bunker can beprevented.

As described above, because the embodiment of the present invention canprevent a defect such as a bunker, the thickness of a storage node canbe decreased. That is, a storage node having a thickness of less than300 Å can be formed. Thus, the present invention can obtain good stepcoverage when a dielectric formation process is performed on the storagenode, and can increase an inner hole area of the storage node in orderto improve electrostatic capacitance of a capacitor.

Furthermore, a second interlayer insulation layer surrounds an outersidewall of the bottom region of a storage node, such that the storagenode does not collapse during a wet dip-out process.

Moreover, a first storage node contact plug protrudes above a firstinterlayer insulation layer, such that a contact area between the firststorage node contact plug and a second storage node contact plug isincreased. Therefore, a contact resistance between the first storagenode contact plug and the second storage node contact plug can bedecreased, thereby improving electrical characteristics.

Because a sufficient electrostatic capacitance is obtained in a limitedarea of a capacitor in a semiconductor device and dual bit fail due to abunker is prevented simultaneously, reliability and a fabricating yieldof the capacitor can be improved.

While various embodiments have been described, it will be apparent tothose skilled in the art that various changes and modifications may bemade.

1. A method for fabricating a semiconductor device, the methodcomprising: forming a storage node contact plug that penetrates aninterlayer insulation layer; forming a separation insulation layer overthe interlayer insulation layer; performing a main etch process to forman open region by selectively etching the separation insulation layer,the open region exposing a top surface of the storage node contact plug;performing an over-etch process to expand the open region by etching thestorage node contact plug and the interlayer insulation layer, therebythe expanded open region extending laterally beyond side surfaces of thestorage node contact plug after the performance of the over-etchprocess; forming a storage node in the expanded open region; andremoving the separation insulation layer.
 2. The method of claim 1,wherein the forming of the storage node contact plug comprises: forminga first interlayer insulation layer including a first storage nodecontact plug; recessing the first interlayer insulation layer topartially protrude the first storage node contact plug above the firstinterlayer insulation layer; forming a second interlayer insulationlayer to cover the first storage node contact plug protruding above thefirst interlayer insulation layer; forming a contact hole to partiallyexpose the first storage node contact plug by selectively etching thesecond interlayer insulation layer; and forming a second storage nodecontact plug by filling the contact hole with a conductive layer.
 3. Themethod of claim 2, wherein the first interlayer insulation layer and theseparation insulation layer comprise an oxide layer.
 4. The method ofclaim 2, wherein the second interlayer insulation layer comprises anitride layer.
 5. The method of claim 2, wherein the first interlayerinsulation layer and the separation insulation layer comprise an oxidelayer and the second interlayer insulation layer comprises a nitridelayer.
 6. The method of claim 2, wherein a thickness of the secondinterlayer insulation layer is less than a thickness of the firstinterlayer insulation layer.
 7. The method of claim 2, wherein thesecond storage node contact plug has a zigzag structure and overlaps thefirst storage node contact plug by a predetermined region.
 8. The methodof claim 2, wherein the first storage node contact plug and the secondstorage node contact plug are formed of the same material.
 9. The methodof claim 8, wherein the first storage node contact plug and the secondstorage node contact plug comprise a polysilicon layer.
 10. The methodof claim 2, wherein an etch depth etched during the performing of theover-etch process is less than a thickness of the second interlayerinsulation layer.
 11. The method of claim 1, wherein the main etchprocess and the over-etch process are performed in-situ.
 12. The methodof claim 1, wherein the storage node includes any one selected from thegroup consisting of titanium nitride (TiN), tantalum nitride (TaN),hafnium nitride (HfN), ruthenium (Ru), ruthenium oxide (RuO₂), platinum(Pt), iridium (Ir), and iridium oxide (IrO₂), or a stack layer thereof.13. The method of claim 1, further comprising forming an ohmic contactlayer between the storage node contact plug and the storage node. 14.The method of claim 13, wherein the ohmic contact layer comprises metalsilicide.
 15. A method for fabricating a capacitor of a semiconductordevice, the method comprising: forming a first interlayer insulationlayer including a first storage node contact plug; partially protrudingthe first storage node contact plug above the first interlayerinsulation layer by recessing the first interlayer insulation layer;forming a second interlayer insulation layer over the first interlayerinsulation layer to cover the protruding first storage node contactplug; forming a contact hole to expose the first storage node contactplug by selectively etching the second interlayer insulation layer;forming a second storage node contact plug by filling the contact holewith a conductive layer; forming a separation insulation layer over thesecond interlayer insulation layer including the second storage nodecontact plug; forming an open region by selectively etching theseparation insulation layer, the second interlayer insulation layer, andthe second storage node contact plug, thereby a bottom portion of theopen region extending laterally beyond side surfaces of the secondstorage node contact plug; forming a storage node in the open region;and removing the separation insulation layer.
 16. The method of claim15, wherein the forming of the open region comprises: performing a mainetch process to form an open region by selectively etching theseparation insulation layer, the open region exposing a top surface ofthe second storage node contact plug; and performing an over-etchprocess to expand the open region by partially etching the secondstorage contact plug and the second interlayer insulation layer at abottom of the open region.
 17. The method of claim 16, wherein an etchdepth etched during the over-etch process is less than a thickness ofthe second interlayer insulation layer.
 18. The method of claim 15,wherein the first interlayer insulation layer and the separationinsulation layer comprise an oxide layer and the second interlayerinsulation layer comprises a nitride layer.